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M65608E
128 K 8 Very Low Power CMOS SRAM Rad Tolerant
Introduction
The M65608E is a very low power CMOS static RAM organized as 131072 x 8 bits. TEMIC brings the solution to applications where fast computing is as mandatory as low consumption, such as aerospace electronics, portable instruments, or embarked systems. Utilizing an array of six transistors (6T) memory cells, the M65608E combines an extremely low standby supply current (Typical value = 0.2 A) with a fast access time at 30 ns over the full military temperature range. The high stability of the 6T cell provides excellent protection against soft errors due to noise. The M65608E is processed according to the methods of the latest revision of the MIL STD 883 (class B or S), ESA SCC 9000 or QML.
Features
D Access time: 30, 45 ns D Very low power consumption active : 250 mW (Typ) standby : 1 W (Typ) data retention : 0.5 W (Typ) D Wide temperature Range : -55 To +125C D 400 Mils width package D D D D D TTL compatible inputs and outputs Asynchronous Single 5 volt supply Equal cycle and access time Gated inputs : no pull-up/down resistors are required
Interface
Block Diagram
Rev. D - June 30, 1999
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M65608E
Pin Configuration
32 pins DIL side-brazed 32 pins Flatpack 400 MILS 400 MILS
Pin Names
A0-A16 I/O0-I/O7 CS1 CS2 W OE VCC GND Address inputs Data Input/Output Chip select 1 Chip select 2 Write Enable Output Enable Power Ground
Truth Table
CS1
H X L L L
CS2
X L H H H
W
X X H L H
OE
X X L X H
INPUTS/ OUTPUTS
Z Z Data Out Data In Z
MODE
Deselect/ Power-down Deselect/ Power Down Read Write Output Disable
L = low, H = high, X = H or L, Z = high impedance.
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M65608E
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : . . . . . . . . . . . . . . . - 0.5 V + 7.0 V DC input voltage : . . . . . . . . . . . . . . . . . GND - 0,3 V to VCC + 0,3 DC output voltage high Z state : . . . . . . GND - 0,3 V to VCC + 0,3 Storage temperature : . . . . . . . . . . . . . . . . . . . . . . -65 C to + 150 C Output current into outputs (low) : . . . . . . . . . . . . . . . . . . . . . . 20 mA Electro statics discharge voltage : . . . . . . . . . . . . . . . . . . . > 2 001 V (MIL STD 883D method 3015.3)
Operating Range
OPERATING VOLTAGE
Military 5 V 10 %
OPERATING TEMPERATURE
- 55 _C to + 125 _C
Recommended DC Operating Conditions
PARAMETER
Vcc Gnd VIL VIH
DESCRIPTION
Supply voltage Ground Input low voltage Input high voltage
MINIMUM
4.5 0.0 GND - 0.3 2.2
TYPICAL
5.0 0.0 0.0 -
MAXIMUM
5.5 0.0 0.8 VCC + 0.3
UNIT
V V V V
Capacitance
PARAMETER
Cin (1) Cout (1) Note :
DESCRIPTION
Input low voltage Output high volt
MINIMUM
- -
TYPICAL
- -
MAXIMUM
8 8
UNIT
pF pF
1. Guaranteed but not tested.
DC Parameters
PARAMETER
IIX (2) IOZ (2) VOL (3) VOH (4) Notes :
DESCRIPTION
Input leakage current Output leakage current Output low voltage Output high voltage
MINIMUM
-1 -1 - 2.4
TYPICAL
- - - -
MAXIMUM
1 1 0.4 -
UNIT
A A V
2. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output Disabled. 3. Vcc min. IOL = 8.0 mA. 4. Vcc min. IOH = -4.0 mA.
Rev. D - June 30, 1999
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M65608E
Consumption
SYMBOL
ICCSB (5) ICCSB1 (6) ICCOP (7) Notes :
DESCRIPTION
Standby supply current Standby supply current Dynamic operating current
65608 - 30
2.5 300 150
65608 - 45
2.5 300 120
UNIT
mA A mA
VALUE
max max max
5. CS1 VIH or CS2 VIL and CS1 VIL. 6. CS1 Vcc - 0.3 V or, CS2 < Gnd + 0.3 V and CS1 0.2 V 7. F = 1/TAVAV, Iout = 0 mA, W = OE = VIH, Vin = Gnd/Vcc, Vcc max.
AC Parameters
Input pulse levels : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gnd to 3.0 V Input rise : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Input timing reference levels : . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output loading IOL/IOH (see figure 1a and 1b) : . . . . . . . . . + 30 pF
AC Test Loads Waveforms
Figure 1a
Figure 1b
Figure 2
Data Retention Mode
MHS CMOS RAM's are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention : 1. . During data retention chip select CS1 must be held high within VCC to VCC -0.2 V or, chip select CS2 must be held low within GND to GND + 0.2 V. 2. Output Enable (OE) should be held high to keep the
RAM outputs high impedance, minimizing power dissipation. 3. During power up and power down transitions CS1 and OE must be kept between VCC + 0.3 V and 70 % of VCC, or with CS2 between GND and GND - 0.3 V. 4. The RAM can begin operation > 45 ns after Vcc reaches the minimum operation voltages (4.5 V).
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Rev. D - June 30, 1999
M65608E
Timing
Data Retention Characteristics
PARAMETER
VCCDR TCDR TR ICCDR1 (10) ICCDR2 (10)
DESCRIPTION
Vcc for data retention Chip deselect to data retention time Operation recovery time Data retention current @ 2.0 V : M-65608 Data retention current @ 3.0 V : M-65608
MINIMUM
2.0 0.0 TAVAV (9) - -
TYPICAL TA = 25 _C
- - - 0.1 0.2
MAXIMUM
- - - 150 200
UNIT
V ns ns A A
Notes :
9. TAVAV = Read cycle time. 10. CS1 = Vcc or CS2 = CS1 = GND, Vin = Gnd/Vcc, this parameter is only tested at Vcc = 2 V.
Rev. D - June 30, 1999
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M65608E
Write Cycle
SYMBOL
TAVAW TAVWL TAVWH TDVWH TE1LWH TE2HWH TWLQZ TWLWH TWHAX TWHDX TWHQX
PARAMETER
Write cycle time Address set-up time Address valid to end of write Data set-up time CS1 low to write end CS2 high to write end Write low to high Z (11) Write pulse width Address hold from to end of write Data hold time Write high to low Z (11)
65608 - 30
30 0 22 18 22 22 8 22 0 0 0
65608 - 45
45 0 35 25 35 35 15 35 0 0 0
UNIT
ns ns ns ns ns ns ns ns ns ns ns
VALUE
min min min min min min max min min min min
Read Cycle
SYMBOL
TAVAV TAVQV TAVQX TE1LQV TE1LQX TE1HQZ TE2HQV TE2HQX TE2LQZ TGLQV TGLQX TGHQZ
PARAMETER
Read cycle time Address access time Address valid to low Z Chip-select1 access time CS1 low to low Z (11) CS1 high to high Z (11) Chip-select2 access time CS2 high to low Z (11) CS2 low to high Z (11) Output Enable access time OE low to low Z (11) OE high to high Z (11)
65608 - 30
30 30 5 30 3 18 30 3 18 12 0 8
65608 - 45
45 45 5 45 3 20 45 3 20 15 0 15
UNIT
ns ns ns ns ns ns ns ns ns ns ns ns
VALUE
min max min max min max max min max max min max
Notes : 11. Parameters guaranteed, not tested, with output loading 5 pF. (see fig. 1.b.).
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Rev. D - June 30, 1999
M65608E
Write Cycle 1. W Controlled. OE High During Write
Write Cycle 2. W Controlled. OE Low
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M65608E
Write Cycle 3. CS1 or CS2 Controlled.
Note :
12. The internal write time of the memory is defined by the overlap of CS1 Low and CS2 HIGH and W LOW. Both signals must be actived to initiate a write and either signal can terminate a write by going in actived. The data input setup and hold timing should be referenced to the actived edge of the signal that terminates the write. Data out is high impedance if OE = VIH.
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Rev. D - June 30, 1999
M65608E
Read Cycle nb 1
Read Cycle nb 2
Read Cycle nb 3
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M65608E
Ordering Information
TEMPERATURE RANGE M M PACKAGE DJ DEVICE - 65608E GRADE V SPEED - 45 FLOW /883
M = Military S = Space
-55 to +125C -55 to +125C
30 ns V = Very low power 45 ns
C9 = DJ = 0=
Side Brazed 32 pins 400 mils Flat Package 32 pins 400 mils die
128K x 8 STATIC RAM
blank /883 SB/SC MQ SV
= = = = =
MHS standards MIL-STD 883 Class B or S SCC 9000 level B/C QML-Q QML-V
The information contained herein is subject to change without notice. No responsibility is assumed by TEMIC for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
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Rev. D - June 30, 1999

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